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Etched
San Jose, United States3 months ago
150,000 – 400,000 USD
per year
Grade
Senior
Experience
from 8 years
Work format
Onsite
English level
B2, upper-intermediate
Relocation
United States, San Jose
An email or a Telegram message to the recruiter
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a Signal & Power Integrity Engineer you will be responsible for the electrical performance of our AI accelerator platform across silicon, package, and board. Intense focus on pushing what is possible in power delivery and high-speed signaling for our silicon.
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.
We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
You will work closely with silicon, package, platform, and system teams to co-design world-class platforms with OSAT and ODM partners.
SI/PI analysis of designs and optimization within 2D/2.5D/3D packages
Close interaction with Package Layout Designers, ASIC PD and IP teams as well as Board Schematic/Layout/SI/PI teams to optimize the best electrical performance
Drive SI requirements into interposer/substrate layout (high-speed routing: 112G/224G) from preliminary design through tape-out
Drive PDN design and decoupling strategy across substrate and interposer, owning DC IR drop, dynamic IR drop, and impedance targets across all rails
Own ball map / C4 / BGA pin assignment from soft freeze through final freeze in partnership with package layout, ASIC PD, and board layout teams
Support board-level SI/PI and rack-level scale-up topology studies, including rack test vehicle design and cable characterization
Participating in cross-functional meetings and design reviews
The ideal candidate will have extensive experience with high-power package and board designs, robust power delivery networks, and high-speed signaling solutions in advanced packaging. You may be a good fit if you have (Must-have qualifications)
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with a strong understanding of signal integrity and power integrity concepts and fundamentals
8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms
Proven experience defining and closing PDN for high-power silicon, including substrate and PCB plane design, decap strategy, and dynamic IR/EM analysis
Experience with developing systems with high-speed interfaces like HBM, SerDes and D2D interfaces
Hands-on expertise with one or more of: ANSYS HFSS / SIwave, Cadence Sigrity (PowerSI / PowerDC), Keysight ADS
Experience with CoWoS or equivalent advanced packaging materials and technologies including interposer SI/PI implications, C4 bump planning, and substrate stack-up trade-offs
Track record of designing and correlating SI/PI test vehicles against silicon measurement during bring-up and lab characterization
Strong analytical and communication skills, comfortable presenting risk, sign-off status, and trade-offs to cross-functional leadership
Deeply creative and able to think from first principles
Strong candidates may also have experience with (Nice-to-have qualifications)
Familiarity with full RTL-to-GDSII context and how PD decisions interact with package and board PDN
Experience with multi-die, 2.5D, or 3D packaging signoff, including chip-package-system (CPS) co-design
Project management experience coordinating across internal teams, OSAT partners, and PCB ODMs
Familiarity with modern ML and LLM model architectures, accelerator architectures, or HPC system design
Startup experience or comfort working in fast-paced environments
Compensation: $150K - $400K per year
Medical, dental, and vision packages with generous premium coverage
Housing subsidy of $2.5k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch and dinner in our office
Unlimited compute budget subject to ROI justification
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills.
Compensation: $150K - $400K per year
About Etched
Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.
Job Summary
As a Signal & Power Integrity Engineer you will be responsible for the electrical performance of our AI accelerator platform across silicon, package, and board. The ideal candidate will have extensive experience with high-power package and board designs, robust power delivery networks, and high-speed signaling solutions in advanced packaging. You will work closely with silicon, package, platform, and system teams to co-design world-class platforms with OSAT and ODM partners. Intense focus on pushing what is possible in power delivery and high-speed signaling for our silicon.
Key Responsibilities
SI/PI analysis of designs and optimization within 2D/2.5D/3D packages
Close interaction with Package Layout Designers, ASIC PD and IP teams as well as Board Schematic/Layout/SI/PI teams to optimize the best electrical performance
Drive SI requirements into interposer/substrate layout (high-speed routing: 112G/224G) from preliminary design through tape-out.
Drive PDN design and decoupling strategy across substrate and interposer, owning DC IR drop, dynamic IR drop, and impedance targets across all rails.
Own ball map / C4 / BGA pin assignment from soft freeze through final freeze in partnership with package layout, ASIC PD, and board layout teams.
Support board-level SI/PI and rack-level scale-up topology studies, including rack test vehicle design and cable characterization.
Participating in cross-functional meetings and design reviews.
You may be a good fit if you have (Must-have qualifications)
Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field with a strong understanding of signal integrity and power integrity concepts and fundamentals.
8+ years of SI/PI experience on high-performance ASIC, processor, or accelerator platforms.
Proven experience defining and closing PDN for high-power silicon, including substrate and PCB plane design, decap strategy, and dynamic IR/EM analysis.
Experience with developing systems with high-speed interfaces like HBM, SerDes and D2D interfaces.
Hands-on expertise with one or more of: ANSYS HFSS / SIwave, Cadence Sigrity (PowerSI / PowerDC), Keysight ADS.
Experience with CoWoS or equivalent advanced packaging materials and technologies including interposer SI/PI implications, C4 bump planning, and substrate stack-up trade-offs.
Track record of designing and correlating SI/PI test vehicles against silicon measurement during bring-up and lab characterization.
Strong analytical and communication skills, comfortable presenting risk, sign-off status, and trade-offs to cross-functional leadership.
Deeply creative and able to think from first principles.
Strong candidates may also have experience with (Nice-to-have qualifications)
Familiarity with full RTL-to-GDSII context and how PD decisions interact with package and board PDN.
Experience with multi-die, 2.5D, or 3D packaging signoff, including chip-package-system (CPS) co-design.
Project management experience coordinating across internal teams, OSAT partners, and PCB ODMs.
Familiarity with modern ML and LLM model architectures, accelerator architectures, or HPC system design.
Startup experience or comfort working in fast-paced environments.
Benefits
Medical, dental, and vision packages with generous premium coverage
Housing subsidy of $2.5k per month for those living within walking distance of the office
Relocation support for those moving to San Jose (Santana Row)
Various wellness benefits covering fitness, mental health, and more
Daily lunch and dinner in our office
Unlimited compute budget subject to ROI justification
How we’re different
Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.
We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.
We compare skills, grade, work format and salary
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