Analog Engineer (Verification and Design)

— Experience in verification and design of analog circuits in Cadence, Synopsys, or Siemens. — You share the idea that most of this work can and should be automated. — You will participate in all stages: agent testing, verification rules, libraries, error analysis. We value your expertise specifically – so that the agent works like a strong engineer.

Looking for people for the team: we are developing AI agents for analog chip design

Who are we?

A stealth-mode American startup, the team consists of RU engineers. We are building an agent system for analog electronics: the agent takes the circuit specification, creates a verification plan, generates testbenches, runs simulations, analyzes errors, corrects them, and outputs the result to Cadence (Virtuoso, Maestro). Stack: frontier LLM, HDL21/Python, ngspice, Spectre, Cadence SKILL.

The project is working: one of our clients has reduced verification runs from approximately 4 hours to 2–5 minutes. Next steps include circuit design, optimization, and physical design.

When applying for any of the vacancies, please attach your resume immediately.

We will discuss the terms in person. Write to: recruiter contact.