Offer for RTL and UVM Engineers in 3 Days

Hiring for the team Semiconductors Applications accepted February 9–22 Format Online

About the Team

We are engaged in fabless development of microprocessors based on the open RISC-V architecture for use in server, telecommunication, and network products, data storage systems, client devices, and more. We cover the full cycle of advanced System-on-Chip (SoC) design, from developing our own processor IP to delivering processors with accompanying software as part of a product solution. We also write system software for RISC-V chips: compilers, simulators, operating systems, and benchmarks.

Areas Where You Are Needed

Wireless Systems & IP

The wireless communication technologies team is involved in end-to-end development of modem IP for modern standards, including cellular, satellite, and other types of wireless communication. Specialists are responsible for product roadmaps, architecture creation, development and integration of communication systems based on proprietary SoCs. They also model device operation, research promising communication technologies, and develop deep expertise in global standards.

IP Dev

Engineers develop and verify architectural solutions for RISC-V-based processor cores, memory subsystems, cryptographic IPs, and networks on chip. In addition to hardware design, specialists create their own verification IP (VIP) to test its functionality, assess performance, and reuse in projects.

SoC

The team is engaged in the design, integration, and delivery of Systems-on-Chip (SoC) based on RISC-V architecture processor cores. Colleagues are responsible for the entire ASIC design flow, including architecture development for future microchips and necessary platform IPs, design integration and verification, and FPGA prototyping. They also develop drivers and embedded software, integrate test DFT structures, perform physical implementation, design packaging, and conduct post-silicon chip testing.

Candidate Requirements

UVM Verification Engineer

Key Responsibilities:

• Develop and implement verification plans.
• Develop, integrate, and support automated verification environments using UVM for IP/SoC.
• Connect, configure, and utilize pre-existing VIPs for standard interfaces.
• Create test scenarios, tests, and system stimuli for functional testing.
• Write SVA and functional coverage, analyze results.
• Integrate modular environments at the system level, set up and maintain regression testing.
• Localize and analyze errors at all levels (from block to system) in collaboration with development teams.
• Interact with architects, RTL engineers, and programmers to ensure product quality.

What we expect from a future team member:

• Experience in digital circuit verification or RTL development, including academic experience.
• Strong knowledge of Verilog/SystemVerilog and practical experience in building verification environments.
• Experience with RTL simulators (VCS, Xcelium, QuestaSim).
• Skills in writing and debugging scripts for task automation (Python/Perl/Tcl/Shell).
• Experience working in a Linux environment and with version control systems (Git).
• Understanding of digital circuit design fundamentals and functional verification principles.
• English language proficiency for reading technical documentation.

Will be a plus:

• Experience with high-speed interfaces (1G Ethernet, PCIe, SATA, USB, DDR3) and/or VIP for them.
• Use of formal verification.
• Ability to work with Xilinx FPGAs.
• Knowledge of C/C++ or ASM programming languages.
• Experience with DPI.
• Knowledge in the field of Digital Signal Processing (DSP).
• Familiarity with modern AMBA interfaces (AXI4/5, AHB, AXI-Lite, AXI-Stream).
• Understanding of the test pyramid, coverage strategies.
• Familiarity with PyUVM, cocotb.
• Experience with Jira and Confluence.

RTL Design Engineer

Key Responsibilities:

• Develop complex functional modules for ASICs using Verilog/SystemVerilog.

What we expect from a future team member:

• RTL development experience of 2+ years.
• Knowledge of Verilog/SystemVerilog.
• RTL simulator usage experience of 2+ years (any vendor).
• Linux experience.
• English language proficiency for reading technical documentation.
• Version control system experience.
• Knowledge of modern interfaces (AXI, APB, AHB).
• Familiarity with peripheral interfaces (SPI, UART, I2C, I3C).

Will be a plus:

• Familiarity with make and scripting languages (perl/python/tcl/shell).
• C/asm programming experience.
• Experience with Altera and/or Xilinx FPGAs.
• Experience developing error-correcting code blocks.
• Knowledge of LTE/5G L1 standards.
• Experience developing and implementing DSP algorithms.
• Experience using Python or MATLAB/Simulink.
• Familiarity with verification methodologies.

What We Offer

• Opportunity to work with international-level professionals.
• Personal involvement in shaping processes and products.
• Engineering experimentation culture.
• Training portal, English language courses, conference participation.
• Voluntary medical insurance from the first day of employment.
• Flexible schedule and remote work option.

About the Company

YADRO is a Russian technology company founded in 2014. It is one of the leaders in the Russian IT infrastructure market, creating a full cycle of computing solutions, from architecture and software development to mass production.