Description

Join our dynamic and talented team, solving ambitious and cutting-edge engineering challenges in the field of high-performance computing system development.

Responsibilities

· Develop, coordinate, and update IP verification plans.

· Develop and debug UVM-based Verification IP and verification environments.

· Develop and debug a coverage model in SystemVerilog.

· Develop and debug direct and constraint-random tests and test sequences.

· File bugs and assist in RTL debugging.

· Monitor current verification status and progress, compile coverage reports.

· Assist in setting up and maintaining the regression run environment.

Requirements

· Experience in the responsibilities listed above in at least one FromSpec2GDS project.

· Knowledge and understanding of Metric Driven Verification aspects.

· SystemVerilog for Verification: OOP, Functional Coverage, Constraint Solver.

· UVM.

· Experience using simulators and Verification IP from vendors among the "big three."

· GIT.

• Ability and willingness to work in a team.

· Ability to independently plan one's work, concisely explain and document results.

· Critical thinking and problem-solving skills.

· Ability to express and effectively communicate one's own ideas to one's own and related teams.

· Ability to approach colleagues with empathy and support, listen to and understand their ideas, different viewpoints, and values.

Optional, but a plus: knowledge of processor architectures, GLS, SVA, DPI, HVP, Bash, make, Python, Jira, Confluence.

Conditions

• Comfortable modern office near Kutuzovskaya metro station, hybrid work format.
• Corporate gym and relaxation areas.
• More than 400 educational programs from SberUniversity for professional and career development.
• Extended voluntary health insurance (VHI), preferential family insurance, and corporate pension program.
• Free SberPrime+ subscription, discounts on products from partner companies.
• Referral bonus for recommending friends to join the Sber team.