Description
Our team tackles ambitious and cutting-edge engineering challenges in the field of high-performance computing system development.
Responsibilities
- Designing DFT architecture and implementing test structures (SCAN, MBIST, BSCAN) for IP blocks, subsystems, and the top level of the System on Chip (SoC)
- Developing timing constraints (SDC) for test modes and analyzing STA reports
- Close cross-team collaboration at all project stages with RTL design and physical design teams
- Generating, simulating, and analyzing test patterns (ATPG) for stuck-at, transition, and other fault models to achieve target test coverage
- Preparing and delivering test patterns to production for testing on Automated Test Equipment (ATE)
Requirements
- Understanding of DFT principles and methodologies: SCAN, MBIST, BSCAN, ATPG
- Ability to read and analyze RTL code for diagnosing and debugging testability issues
- Hands-on experience with DFT tools (Synopsys TetraMAX/TestMAX, Cadence Modus, Siemens Tessent)
- Hands-on experience with logic synthesis tools (Synopsys Design Compiler/Fusion, Cadence Genus)
- Hands-on experience with logic simulation tools (Synopsys VCS, Cadence Xcelium)
Will be a plus:
- Understanding of the basics of Static Timing Analysis (STA) and formal verification
- Knowledge and practical application of IEEE 1149.1, IEEE 1500, IEEE 1687 standards
- Experience with Automated Test Equipment (ATE) or interaction with production test engineers
- Experience with version control systems (Git)
- Scripting skills in Tcl, Python, Shell for task automation
Conditions
- Comfortable modern office near Kutuzovsky Prospekt metro station, hybrid work format
- Corporate gym and relaxation areas
- Over 400 educational programs from SberUniversity for professional and career development
- Extended voluntary health insurance, preferential insurance for family, and corporate pension program
- Free SberPrime+ subscription, discounts on products from partner companies
- Referral bonus for recommending friends to the Sber team.
