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Grade
Middle
Experience
from 3 years
Work Format
Hybrid, Onsite
English Level
B2 - Upper-Intermediate
By country
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in a Russian tech company.
The company considers candidates from the Russian Federation and Belarus. Salary: discussed, social package. Work format: Hybrid, Office, (Moscow, St. Petersburg, Nizhny Novgorod, and Minsk); Position level: Middle, Senior
Stack: SystemVerilog, UVM;
🔷Tasks: Planning functional verification and developing test plans for IP blocks or SoC; Developing verification environments for IP blocks developed by the company; Automating the testing procedure using scripting languages; Regression testing in CI systems; Interaction with IP block developers, architects, and programmers at all stages of verification; Connecting and configuring VIP for various devices and interfaces; Setting up for regression testing.
🔷Mandatory requirements: Experience in verification and/or RTL development for FPGA or ASIC, from 3 years. Familiarity with the architecture of at least one modern processor; Proficient user of an RTL simulator (any vendor); Good knowledge of SystemVerilog and its OOP subset; Proficiency in scripting languages (perl/python/tcl/shell scripting); Proficient user of Linux; English language proficiency at the level of reading technical documentation and ability to conduct correspondence on technical topics.
Will be an advantage: Familiarity with UVM; Programming experience in ASM, C; Experience with Continuous Integration systems; Familiarity with modern SoC interfaces (AXI, AHB, OCP, CHI).
